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Verilog Computer-Based Training Course By Zainalabedin Navabi

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Sales Rank: #3432029 in eBooks
Published on: 2002-05-21
Released on: 2002-05-21
Format: Kindle eBook
Number of items: 1

From the Back Cover
teach yourself the fastest-growing HDL -- hands down and hands on.

. Learn Verilog with an Interactive Tutor.

. Save over 90% of the cost of online courses or single-day seminars!.

. COMPLETE SELF-TEACHING COURSE AND VERILOG REFERENCE.

. You can learn Verilog at your own pace with this comprehensive, up-to-date, and powerful CD-ROM training course. Start at the beginning with the development of Verilog code and the application of HDL-based tools in simulation, synthesis, verification, and testing or digital systems�or jump in anywhere if you already know some of the material. There�s more. This resource-loaded CD will be an indispensable reference for as long as you use Verilog�and for anyone currently working in this rapidly growing HDL. The CD includes templates for common RT-level components and has complete Verilog code for parallel and serial interface devices and arithmetic units such as array multipliers, pipeline dividers and polynomials. The topic of test benches and test bench generation in Verilog is completely covered in this CD..

. Verilog Computer-Based Training Course CD-ROM features:.
*everything you need to learn Verilog, in an interactive environment.
*hundreds of worked examples and self-test problems from easy to complex.
*test bench for every example and test bench templates for complex circuits.
*quality Verilog simulator that runs all examples.
*live links to working Verilog models and references.
*quick access to the exact model, template, data, syntax, or grammar you need.
*60-page user�s manual with answers to all problems and simulations.
*projects at the end of each subject.
*quizzes at the end of topics.

. the first CBT self-tutor in Verilog.

.
*Always statement.
*Assign statements.
*Assign and deassign.
*Blocking assignment.
*Case statement.
*Delay control.
*Display.
*Edge detection.
*Event control.
*Force and release.
*Fork and join.
*Formal grammar.
*Function definition.
*Hierarchical names.
*If statement.
*Intra assignment delay.
*Language constructs.
*Memory.
*Net types.
*Nonblocking assignment.
*Parameters.
*Path delay.
*PLA modeling.
*Procedural blocks.
*Registers.
*Setup and hold check.
*Specify block.
*Strength modeling.
*Syntax.
*Synthesizable code.
*System tasks.
*Task declaration.
*Test benches.
*Timing check.
*Timing control.
*Trireg.
*Wait statment.

. CIRCUIT DESCRIPTIONS.

.
*Array multiplier.
*Associative memory.
*Asynchronous control.
*Bus arbiter.
*Busses.
*Carry look-ahead adders.
*Circuit templates.
*Combinational circuits.
*Combinational UDPs.
*Controllers and state machines.
*Controllers testing.
*Data path testing.
*Exhaustive testing.
*External file handling.
*FIFO quieues .
*Fault tolerant adders.
*Flip-flops .
*Gate-level blocks.
*IEEE 1149.1.
*Iterative circuits.
*LFSR.
*LRU.
*Logic gates.
*MISR.
*Memory parts.
*Pipeline divider.
*Registers.
*Register files.
*Sequential UDPs.
*Shifter-counters.
*Stacks.
*System architectures.
*Switch level logic.
*TAP controller.
*Test benches.
*UART.
*Wired logic

About the Author
Zainalabedin Navabi, Ph.D., is professor of electrical and computer engineering at Northeastern University and the author of Verilog Digital System Design and both editions of VHDL: Analysis and Modeling of Digital Systems, all published by McGraw-Hill. Since 1981, Dr. Navabi has worked in the design, definition, and implementation of hardware description languages and the synthesis and testing of digital systems. He has developed and supervised the development of many HDL-related software packages and tools, and has directed projects in VLSI design, test synthesis, simulation, synthesis, and other aspects of digital system design automation. He has served as a consultant for several EDA companies developing HDL-based tools and environments. Dr. Navabi is a member of ACM, IEEE, and IEEE Computer Society, and is an active participant in the IEEE DASC committee that sets standards related to hardware description languages.

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